The applicants claim priority under 35 U.S.C. xc2xa7119 of German application Nos. 19714756.9 and 19731043.5 filed on Apr. 10, 1997 and Jul. 19, 1997. The applicants claim priority under 35 U.S.C. xc2xa7120 of PCT/DE98/01019 filed on Apr. 8, 1998. The international application under PCT article 21(2) was not published in English.
The invention relates to a method for designing complex digital integrated circuits for ensuring a testability of at least 95% error coverage with automatically generated test patterns.
Complex digital integrated circuits (ASICs) are in general comprised of pulse controlled element, hereinafter referred to as registers, RAM structures, as well as combinatorial elements. Methods for the design of complex digital integrated (ASICs comprise the following basic method steps:
preparation of a specification of the ASIC to be designed
implementation of the specification with HDL languages, for example VHDL (HDL: hardware distribution language)
production of the ASIC circuit by means of ECAD software verification and delivery to the production/manufacture of the ASIC circuit.
The testability of an ASIC is required during the production phase of the ASIC so as to recognize in very short time defects that have arisen during the manufacture and to separate the ASIC which have defects.
The error coverage of an ASIC is the yard stick of how many internal line nets of an ASIC have to be subjected to quality control relating to defects during manufacture, particularly short circuit errors. The yard stick, also test coverage, is in practical experience about 95% of all internal line nets of an ASIC.
Test patterns describe cyclic condition sequences, which are applied at the input lines of an ASIC and which are awaited at the output lines of an ASIC in the event of an absence of errors.
Automatically generated test patterns are formed by test pattern generators, hereinafter ATPG (automatic test pattern generator). These ATPG are available as ECAD software or circuit-technologically realized, for the installation in the ASIC, for example, BIST cells (BIST: built-in-self-test). So that ATPG for a complex ASIC test pattern with high error coverage can compute, test structures need to be implemented (Literature reference: xe2x80x9cSelftest Digital Circuits,xe2x80x9d M. Gerner/B. Mxc3xcller/G. Sandweg, Publisher Oldenburg.)
In hitherto known design methods of ASICs, after the generation of the specification, which is in written form or already as model of the system, the circuit is produced, in that the detailed system implementation is done, via the combining of register, RAM structures, as well as combinatory elements is carried out in the equivalent sense.
In the case of a specification in written form the entire system is usually divided into a plurality of subsystems which, via HDL languages, are realized as sub modules with RTL syntax (RTL: register transfer level).
In the case of manual implementation these sub modules are verified separately, prior to incorporation into the overall design. When using automatic methods (U.S. Pat. No. 5,598,344), realized as ECAD software, there also is done a dividing operation (partitioning) of the entire system.
When the specification is at hand in the form of a suitable system model the synthesis-ready RTL model can be produced with ECAD tools, for example behavioral compiler of the firm Synopsys, Inc. (xe2x80x9cBehavioral Compiler Methodology Note,xe2x80x9d Version 3.3a, April 1995, Synopsys, Inc.).
After one of the two outlined procedures has been concluded and the synthesis of the completed RTL model has been done, the circuit structure is at hand in the form of registers, combinatorial elements, RAM modules.
With this prerequisite the test structures can be fixed as to detail so as to ensure a utilization of ATPGs for the generation of test patterns with defined error coverage. This is done by inclusion of special test registers (scan registers), automatic test generators, especially for RAM cells (BIST cells). Also for this problem there exist automatic methods, for example, in U.S. Pat. No. 5,463,562, in which through automatic introduction of registers a testability of a circuit is to be attained. The inclusion of text multiplexers (test structures: see method claim 2) into an already finished implemented circuit structure (RTL design with connected registers and combinatorial elements), according to specified circuit function, described in xe2x80x9cDesigns for Hierachrical Testability of RTL Circuits Obtained by Behavioral Synthesis,xe2x80x9d Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha, International Conference on Computer Design: VLSI in Computers and Processors, Austin, Oct. 2-4, 1995, Oct. 2, 1995, pages 173-179, Institute of Electrical and Electronics Engineers, avoids the appearance of non-testable areas in the design, for example, signals with constant signal level, combinatorial re-coupling and so on. It is to be remarked that this inclusion can only then arise when the time intensive system implementation (method step d)) has been done. Furthermore, other important design parameters, such as clock-skew, the effort consumption through method are not addresses since the method does not influence the structure/connection of the registers of the circuit structure to be changed. Another embodiment of realization of these automatic methods is the ECAD software test compiler of the firm Synopsys, Inc.
Due to the high specific area requirements of such test structures, particularly in the case of large ASIC circuits, in praxis one has developed the manner to use manually produced functional test patterns for attainment of the error coverage. For this purpose the firm Siemens AG developed the program system TOPS which guarantees that patterns produced during the system simulation are cycle oriented and, thus, test acceptable. These functional test patterns need to be examined, however, in a lengthy test simulation respective to their suitability of the error coverage.
In summary, it can be mentioned that in all known methods the structure of pulse controlled or storing elements, so register or RAM cells, to the finished productionof the circuit inclusive of the test structures in quantity and structure are not fixed. However, the just mentioned circuit elements affect in quantity and structure important ASIC design goals, such as testability, the execution/performance consumption, the requirement as to area, as well as the production effort in the layout phase.
Thus, the following points of criteria are seen in hitherto known design methods for ASICs:
1. Estimation of the circuit or, respectively, the project course, or the project cost, as criterion of the provision of development orders on the part of the customer are unclear at the commencement of the design. Particularly this applies to the required area as well as the performance consumption, since the amount of registers and RAM modules of the circuit is known just prior to delivery. There exists the danger of customer dissatisfaction, in some cases even the non-acceptance of the circuit by the customer. These risks cause direct or indirect high cost.
2. There exists the danger of a delayed delivery of the test patterns, Therewith in the ASIC production the production quality can not, be sufficiently subject to quality control examinations. Particularly then when using functional test patterns the suitability of which for error coverage needs to be examined in lengthy test siulations. Particularly this point needs to be observed in praxis. Through the delays of the production also arise high cost and dissatisfaction of the customer.
By using the method according to the invention as well as the circuit structure, it is possible to achieve the stated goals of the invention. The establishment of the register structures and RAM structures that are independent of functional implementation as shown in FIG. 1 box no. 3 relate to the definition of the clock structures as established in FIG. 1 box no. 4. With this prerequisite, the layout activities for the register structures and RAM structures can now be brought to a conclusion. This also includes verification of the register structures and RAM structures with regard to clock skew. In this connection it is obvious that the clock skew is significantly less than in comparable circuits since the RAM structures can be arranged in the layout with special separation from the combinatory elements, the implementation of which is generally complicated and time consuming, has no influence on clock skew, independent on how complex the system function based upon the specification. This also applies to the production test, since the fixed, defined number of register levels guarantees a uniform controllability i.e. observability of all the networks between the combinatory elements.
In contrast to special circuits, the circuit structure according to the invention as shown in FIG. 2 and FIG. 5, allows flexibility of the overall function of the ASIC after production. Selected functions can be structured so as to be configured via the RAM and selected using a microcode, via loading of the RAM.
In the method according to the invention qualified estimation of the required area, performance effort are to be possible, prior to implementing the system in detail to specifications. Thereby it is possible to advise the customer in an early phase of the design concerning the significant values/parameters, such that the customer is in a position to react in early manner.
Furthermore, during an early phase is to be ensured that the generation of the test patterns with an at least coverage of 95% exclusively known ATPGs are used. Special test problems need to be solved at an early stage.
One object of the invention is to use a method for designing digital ASIC circuits as well as a circuit structure for implementing the method, a circuit structure for processing several coded data streams (GSM, DECT, ATM, MIMD, etc.) which can also be implemented as a digital signal processor (DSP).
The goal of the invention is a compromise between the advantages of the stated design methods.
With regard to special circuits, complications in the ASIC layout (1) and the final verification are supposed to be avoided; these complications increase with the functional implementation of complex processing tasks. The following measures relate to these complications in the ASIC layout and are supposed to be carried out independently i.e. separate from the functional implementation of the specification:
Definition of the test structures and clock structures;
Definition of the number of register levels for verification of critical layout parameters, such as clock screw;
Furthermore, circuits according to the invention are supposed to have a flexibility of function after completion of the ASIC similar to DSP. With regard to MPS, the invention is supposed to have the following advantageous characteristics: 1) complete functional implementation of the specification with HDL models; and higher cycle frequency.
The aim is solved in accordance with the invention according to patent claim 22. The patent claims 23 to 27 refer to advantageous embodiments of the invention.